DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 109

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Memory Modes
Figure 2–14. Shift-Register Memory Configuration
May 2011 Altera Corporation
ROM Mode
FIFO Mode
f
1
w
W
W
W
W
×
m
Figure 2–14
All Stratix V embedded memory blocks support ROM mode. A .mif initializes the
ROM contents of these blocks. The address lines of the ROM are registered on M20K
blocks; however, they can be unregistered on MLABs. The outputs can be registered
or unregistered. Output registers can be asynchronously cleared. The ROM read
operation is identical to the read operation in the single-port RAM configuration.
All Stratix V embedded memory blocks support FIFO mode. MLABs are ideal for
designs with many small, shallow FIFO buffers. You can use the FIFO MegaWizard
Plug-In Manager to implement FIFO buffers in your design. The FIFO MegaWizard
Plug-In Manager supports single- and dual-clock (asynchronous) FIFO buffers.
For more information about implementing FIFO buffers, refer to the
DCFIFO Megafunctions User
MLABs do not support mixed-width FIFO mode.
×
n Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the embedded memory block in shift-register mode.
Guide.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
W
W
W
W
n Number of Taps
SCFIFO and
2–15