ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 107

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.10: PCINT ROM Base Address
This register specifies the base address of where in PCI memory space the IBM3206K0424 ROM will be
mapped. When written with ones and read back, the least significant bits read back as ’0’ will indicate the
amount of memory space required for this device to operate. For example, when a value of ’FFFFFFFF’ is
written, a value read of ’FFFFFF00’ indicates that 256 bytes of address space is required. See bit definitions.
Length
Type
Address
Restrictions
Power on Reset value
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31-10
Bit(s)
9-1
0
PCI Spec
31-11
10-1
0
Reserved
Address Decode Enable
Base Address
32 bits
Read/Write
XXXX 0030
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as Big Endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
X’00000000’
Base Address
Name
This register is used to hold the address where the target device will
decode for expansion ROM. The size is fixed at 2K of addressing, natu-
rally aligned.
Reserved and set to ’0’.
This bit set to ’1’ will enable accesses to expansion ROM only if Memory
Space Enable bit (bit 1 in PCINT Configuration Word 1) is also set.
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
Description
9
8
7
Reserved
6
5
4
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IBM3206K0424
3
2
1
0