ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 98

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
IBM3206K0424
IBM Processor for Network Resources
1.4: PCINT Config Word 3
This word specifies the system cache size in units of 32-bit words, the value of the Latency Timer for this PCI
bus master, the Header Type which identifies the layout of bytes in configuration space, and the register for
the control and status of BIST (Built-in self-test). See bit definitions.
Length
Type
Address
Restrictions
Power on Reset value
(Big Endian)
Power on Reset value
(Little Endian)
The IOP Bus Specific Interface Controller (PCINT)
Page 98 of 676
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
29-28
27-24
23-16
Bit(s)
15-8
7-0
31
30
PCI Spec
Completion
5-4
3-0
7-0
7-0
7-0
7
6
Code
BIST Capable
Start BIST
Reserved
Completion Code
Header Type (Read Only)
Latency Timer
Cache Line Size
32 bits
Read/Write
XXXX 000C
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
X’80000000’
X’00000080’
Header Type (Read Only)
Name
This bit is a ’1’ because this device supports BIST.
Writing this bit ’1’ invokes BIST. This bit is reset to ’0’ after BIST is com-
plete. This bit has two seconds to reset after a start BIST action.
Reserved
A value of ’0’ means this device has passed BIST. If bit 27 is on, the
PRPG value failed. If bit 26 is on, the MISR value failed. Bits 25 and 24
are always ’0’.
The encoding chosen is X’00’.
This register specifies a value of latency in units of PCI bus clocks.
This register is used to best determine what read command should be
used by this master. Any cache line size is supported.
Latency Timer
Description
8
7
6
Cache Line Size
5
4
pnr25.chapt04.01
August 14, 2000
3
Preliminary
2
1
0

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