ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 93

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Internal Organization: Entity Descriptions
This part contains detailed descriptions of the entities which, working together, make up the IBM3206K0424.
The data flows through the chip have already been described; now the details of the registers and algorithms
will be revealed. The entity descriptions are numbered for easy reference.
Note on Set/Clear Type Registers
There are many registers in IBM3206K0424 that operate as a set/clear type. These registers have two
addresses. The base address is for clearing bits in the register, and base address +4 bytes is for setting bits
in the register. The setting or clearing operations occur only for those bits that have the value of’1’ on the write
of the register. Either of the addresses can be used for reading the register.
Control Processor Bus Interface Entities
Entity 1: The IOP Bus Specific Interface Controller (PCINT)
This entity provides PCI specific interfacing between the external connection and the internal entities. It will
support the following functions:
PCI Options Taken
PCI Target Response
PCI Master Response
pnr25.chapt04.01
August 14, 2000
• PCI memory target
• PCI master
• Address and data latching
• Provide parity error detection and generation
• Provide configuration space registers
• 64-bit data path for master and slave operation
• 64-bit addressing support for master and slave operation
• Auto 64-bit slot detection supported
• 66MHz PCI bus clock operation supported
• Medium address decode design point
• Locking as a memory target supported
• Interrupt A will be supported, with interrupt 2 as a the sideband signal
• Registers will not burst, but cause retries when a burst is attempted
• BIST defaults set at the PCI 2 second maximum
• A Target Retry is issued if a burst crosses the end of the IBM3206K0424’s memory space.
• A Target Abort will be issued if AD and command bus have bad parity (address phase parity error).
• If enabled, the PERR signal will be driven on bad parity during data write cycles (data phase parity error)
• A Target Retry will be issued by the IBM3206K0424 if internal contention will cause a large bus access
• A Master Abort will be issued if DEVSEL is not asserted after five clocks.
• If enabled, the PERR signal will be driven on bad parity during data read cycles (data phase parity error)
Optionally, if SERR is enabled, it will also be returned.
when the IBM3206K0424 is the target of the command.
delay.
when the IBM3206K0424 is the initiator of the command.
.
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
IBM3206K0424
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