ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 163

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt04.01
August 14, 2000
Bit(s)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Error Enqueuing Descriptor
DMA Descriptor Error
DMA Descriptor Queue 2
Not Full
DMA Descriptor Queue 2
Threshold Exceeded
DMA Descriptor Queue 2 Full
DMA Descriptor Queue 1 Not
Full
DMA Descriptor Queue 1
Threshold Exceeded
DMA Descriptor Queue 1 Full
DMA Descriptor Queue 0 Not
Full
DMA Descriptor Queue 0
Threshold Exceeded
DMA Descriptor Queue 0 Full
Error Occurred During Descrip-
tor Transfer
Error Occurred During DMA
Transfer Q2
Error Occurred During DMA
Transfer Q1
Error Occurred During DMA
Transfer Q0
DMA Transfer Complete Q2
DMA Transfer Complete Q1
DMA Transfer Complete Q0
Function
A descriptor was enqueued with a chain length of zero.
An invalid transfer was described by the value loaded into the Transfer Count and Flag reg-
ister.
The DMA descriptor Queue 2 is not full. This bit always contains the status of the queue
and is therefore is not writable.
The threshold for DMA descriptor Queue 2 has been exceeded.
The DMA descriptor Queue 2 is full. This bit always contains the status of the queue and is
therefore is not writable.
The DMA descriptor Queue 1 is not full. This bit always contains the status of the queue
and is therefore is not writable.
The threshold for DMA descriptor Queue 1 has been exceeded.
The DMA descriptor Queue 1 is full. This bit always contains the status of the queue and is
therefore is not writable.
The DMA descriptor Queue 0 is not full. This bit always contains the status of the queue
and is therefore is not writable.
The threshold for DMA descriptor Queue 0 has been exceeded.
The DMA descriptor Queue 0 is full. This bit always contains the status of the queue and is
therefore is not writable.
Hardware errors occurred transferring the DMA descriptor. The transfer stopped after
detecting the error. If the descriptor transfer is finished or is to be terminated, the byte
count register must be written to clean up the failed descriptor transfer. Before this bit is
reset, the DMA descriptor queue must contain the valid descriptor data or the &regdmt-
dqcn. must be written to the value it contained prior to the descriptor enqueue.
Hardware errors occurred during the last transfer on Queue 2. The transfer stopped after
detecting the error. Inspect GPDMA registers for actual location of error.
Hardware errors occurred during the last transfer on Queue 1. The transfer stopped after
detecting the error. Inspect GPDMA registers for actual location of error.
Hardware errors occurred during the last transfer on Queue 0. The transfer stopped after
detecting the error. Inspect GPDMA registers for actual location of error.
The DMA transfer has completed for Queue 2.
The DMA transfer has completed for Queue 1.
The DMA transfer has completed for Queue 0.
Description
IBM Processor for Network Resources
DMA QUEUES (DMAQS)
Page 163 of 676
IBM3206K0424