ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 311

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
11.6: SEGBF Interrupt Enable Register
This register allows the user to selectively determine which bits in the SEGBF status register will cause
processor interrupts. A ’0’ in a bit position masks interrupts from the corresponding bit location in the SEGBF
status register. A ’1’ in a bit position allows interrupts for the corresponding bit in the SEGBF status register.
See Note on Set/Clear Type Registers on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
11.7: SEGBF Programmable Counters
This register provides the user with feedback on the number of times that a particular event or condition has
occurred in the segmentation logic. The event or condition that causes this counter to increment is defined by
the associated SEGBF Programmable Counter Source Specification register. When the counter wraps, an
event is generated.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt05.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit(s)
31-0
These bits contain a count of the occurrences of the desired event or condition.
12 bits
Clear/Set
XXXX 1420 and 424
X’00’
None
32 bits
Read/Write
Counter 0
Counter 1
Counter 2
Counter 3
X’0000 0000’
None
XXXX 1430
XXXX 1434
XXXX 1438
XXXX 143C
Count of Occurrences
Description
IBM Processor for Network Resources
ATM Transmit Buffer Segmentation (SEGBF)
9
8
7
6
5
4
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IBM3206K0424
3
2
1
0