ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 52

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
:
PHY Bus Pin Descriptions
ATM PHY Bus Interface
Page 52 of 676
Note: Because some of the PHY transmit I/Os are used for receive framer functions and vice versa, there are some restrictions on how
the interfaces can be used.
Quantity
1. If the transmit path is using an external PHY and the receive path is using the internal framer, FYTPAR(1) will assume the OOF
2. If the receive path is using an external PHY and the transmit path is using the internal framer, FYRPAR(1) will assume the OFPtx-
3. If the transmit path is using an external PHY and the receive path is using the internal framer, and the external PHY has a 16-bit
16
16
2
1
1
1
1
1
2
function and not be available as a parity output. This is only a concern if the PHY uses a 16-bit data interface and parity is being
used.
LPow function and not be available as a parity input. This is only a concern if the PHY uses a 16-bit data interface.
data interface, then the receive HDLC interface cannot be used. The three I/O for the RX HDLC interface will instead take on the
function of FYTDAT(15-13).
FYTDAT (15 - 0)
FYRDAT(15 - 0)
FYTPAR (1 - 0)
FYRPAR(1 - 0)
FYnTENB
FYnRENB
Pin Name
FYRRDB
FYTWRB
FYTSOC
Input/Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
(Page 1 of 3)
PHY Transmit Data
Transmit Data Parity
Transmit start of Cell
Transmit write strobe
Transmit write enable
Receive write enable
Receive ready strobe
PHY Receive Data
PHY Receive Data Parity
Pin Function
When using an external PHY, this 16-pin bus carries the ATM
CELL octets that are loaded in the PHY Transmit FIFO. When
using the internal framer, bits 15, 14, and 13 are used for the
RX HDLC interface signals OFPrxR1Data, OFPrxR1DS, and
OFPrxRclk, respectively.
When using an external PHY, these are byte parity signals for
FYTDAT. When using the internal framer, bit 1 provides the RX
Out-Of-Frame indication, OOF, and bit 0 provides the optical/
electrical module transmit shutdown control signal, OFPtxS-
Down. When using a POS-PHY, bit zero provides the TERR
signal.
When using an external PHY, this indicates the start of cell on
FYTDAT. When using the internal framer, this provides the TX
HDLC interface signal, OFPtxT1Dclk. When using a POS-PHY,
this indicates TSOP.
When using an external PHY, this signal is used to write ATM
cells to the transmit FIFO. When using the internal framer, this
signal provides the 19.44MHz TX clock, RefClkT. When using
a Utopia Cell or POS-PHY interface, this signal provides the
write clock based on the clock received on the TXCLK pin.
When using an external PHY, this indicates that transmit data
to the PHY is valid. When using the internal framer, this pro-
vides the TX HDLC interface signal, OFPtxT1DS.
When using an external PHY, this indicates to the PHY that the
IBM3206K0424 is ready to accept data. When using the inter-
nal framer, this provides the clock recovery reset signal,
RSTCRec1.
When using an external PHY, this is used to read ATM cells
from the PHY receive FIFO. When using the internal framer,
this signal provides the 19.44MHz RX clock, RxByClk. When
using a Utopia Cell or POS-PHY interface, this signal provides
the write clock based on the clock received on the RXCLK pin.
When using an external PHY, this 16-pin bus carries the ATM
CELL octets that are read from the PHY Receive FIFO.
When using an external PHY, these are byte parity signals for
FYRDAT. When using the internal framer, bit 1 provides the
optical/electrical module low power indication signal, OFPtx-
LPow, and bit 0 is not used. When using a POS-PHY, bit 0
should be connected to RERR.
Pin Description
pnr25.chapt02.01
August 14, 2000
Preliminary