ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 53

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
PHY Bus Pin Descriptions
pnr25.chapt02.01
August 14, 2000
Note: Because some of the PHY transmit I/Os are used for receive framer functions and vice versa, there are some restrictions on how
the interfaces can be used.
Quantity
1. If the transmit path is using an external PHY and the receive path is using the internal framer, FYTPAR(1) will assume the OOF
2. If the receive path is using an external PHY and the transmit path is using the internal framer, FYRPAR(1) will assume the OFPtx-
3. If the transmit path is using an external PHY and the receive path is using the internal framer, and the external PHY has a 16-bit
1
1
1
1
1
5
5
1
function and not be available as a parity output. This is only a concern if the PHY uses a 16-bit data interface and parity is being
used.
LPow function and not be available as a parity input. This is only a concern if the PHY uses a 16-bit data interface.
data interface, then the receive HDLC interface cannot be used. The three I/O for the RX HDLC interface will instead take on the
function of FYTDAT(15-13).
FYRADR(4-0)
FYTADR(4-0)
Pin Name
FYRSOC
FYREOP
FYRCA
FYnFUL
FYTCA
FYEMP
Input/Output
Output
Output
Input
Input
Input
Input
Input
Input
(Page 2 of 3)
PHY Receive Address
PHY Transmit Address
PHY Receive EOP
Receive start of Cell
Receive Cell Available
Transmit Cell Available
PHY Transmit Full
PHY Receive Empty
Pin Function
When using an external PHY, this signal indicates the start of
cell on the FYRDAT bus.
When using an external PHY, this indicates that a cell is avail-
able in the receive FIFO. When using an internal framer, this
signal is not used. When using a POS-PHY, this signal must be
connected to PRPA.
When using an external PHY, this indicates that a cell is avail-
able in the PHY transmit FIFO. When using the internal framer,
this provides the TX HDLC interface signal, OFPtxT1Data.
When interfacing to POS-PHY, this signal should be connected
to PTPA.
When using an external PHY, this is asserted low by the PHY
when it can accept no more than four more data transfers
before it is full. This pin should be pulled up to the inactive state
when using a PHY that does not drive it. When using the inter-
nal framer, this provides the TX HDLC interface signal,
OFPtxT1DFrm. When using a POS-PHY interface, this signal
must be connected to STPA
When using an external PHY, this is asserted low by the PHY
to indicate that in the current cycle there is no valid data for
delivery to the IBM3206K0424. When the PHY does not drive
FYEMP, this input should be tied to the inactive state. When
using the internal framer, this signal is not used. When using a
POS-PHY interface, this signal is connected to RVAL.
When using an external PHY (Cell or POS-PHY based), this
address is used to select and poll up to 31 PHYs on the receive
side. Bits (1-0) are used to select which of the four PHYs and
bit two is used to indicate the null address. When bit two is B’1’,
bits 1-0 are also ’1’. When bit 2 is ’0’, bits 1-0 are “00”, “01”,
“10”, or “11”.
When using an external PHY (Cell or POS-PHY based), this
address is used to select and poll up to 31 PHYs on the trans-
mit side. Bits (1-0) are used to select which of the four PHYs
and bit two is used to indicate the null address. When bit two is
’1’, bits 1-0 are also ’1’. When bit 2 is ’0’, bits 1-0 are “00”, “01”,
“10”, or “11”.
When using an external POS-PHY, this signal indicates if the
FYRDATA (15-0) contains the last data of a packet. If the
external PHY is not a POS-PHY, this signal should be tied to
GND.
IBM Processor for Network Resources
Pin Description
ATM PHY Bus Interface
IBM3206K0424
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