ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 225

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
7.10: ARBIT Control Config Register
The bits in this register control the operation of the Control Memory arbiter.
Length
Type
Address
Power On Value
Restrictions
7.11: ARBIT Packet Priority Resolution Register High
The bits in this register define the priority of requesting entities to Packet Memory.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt04.01
August 14, 2000
3
Bit(s)
3-2
1
0
2
1
Reserved
This bit controls the arbit entity state debug mux. When set, the incoming entity requests and outgoing acknowledges are
routed to the entity state pins. When reset, the internal state information is routed to the entity state pins.
When set, this bit forces all operations to Control Memory to be serialized. An operation from one entity must be entirely
complete before an operation from another entity will be started. When reset, if the memory operation in process can be
overlapped, a second operation will be started before the first operation is complete.
0
4 bits
Clear/Set
XXXX 0E38 and 3C
X’0’
None
28 bits
Read/Write
XXXX 0E80
X’EDC BA98’
None
Description
ATM Packet/Control Memory Arbitration Logic (ARBIT)
IBM Processor for Network Resources
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IBM3206K0424