ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 112

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
The IOP Bus Specific Interface Controller (PCINT)
Page 112 of 676
15-12
Bit(s)
11-8
7-4
3-0
20
19
18
17
16
Disable retrying on the 1st cycle of
a memory access.
Enable writing to special config
registers
Disable Incremental Latency time-
out retries
Enable PCINT Base Address 1
(I/O for regs)
Enable PCINT Base Address 2
(Mem for regs)
Encoded Control for PCINT Base
Address 6 (Memory)
Encoded Control for PCINT Base
Address 5 (Memory)
Encoded Control for PCINT Base
Address 4 (Memory)
Encoded Control for PCINT Base
Address 3 (Memory).
Function
Setting this bit to ‘1’ disables the retrying of a memory access to IBM3206K0424. This
causes a PCI spec violation, but not a data integrity problem. It solves the rare problem
in which two masters are accessing Control Memory at the same time and retries hap-
pen to both endlessly.
Setting this bit to ’1’ enables writing to certain registers that are normally read-only. An
example of this is the vendor and function ID register (PCINT Configuration Word 0).
Setting this bit to ’1’ disables PCI retries due to cycles taking more than eight cycles on
burst accesses after the first access.
Setting this bit to ’1’ enables PCINT Base Address 1 (I/O for registers). This does the
same function as bit 0 in the PCINT Configuration Word 1 register, but also makes the
PCINT Base Address 1 (I/O for regs) read back ’0’s even when written to with values.
It guards against anything that BIOS code may do to PCINT Configuration Word 1 reg-
ister bit 0 if I/O accesses are not desired.
Setting this bit to ’1’ enables PCINT Base Address 2 (Mem for regs) so IBM3206K0424
registers can be accessed by PCI memory cycles.
Same as bits 3-0.
Encoding of bits:
X'0': Disable this Base Address.
X'1': Configured to respond to a 2 GB address size.
X'2': Configured to respond to a 1 GB address size.
X'3': Configured to respond to a 512 MB address size.
X'4': Configured to respond to a 256 MB address size.
X'5': Configured to respond to a 128 MB address size.
X'6': Configured to respond to a 64 MB address size.
X'7': Configured to respond to a 32 MB address size.
X'8': Configured to respond to a 16 MB address size.
X'9': Configured to respond to a 8 MB address size.
X'A': Configured to respond to a 4 MB address size.
X'B': Configured to respond to a 2 MB address size.
X'C': Configured to respond to a 1 MB address size.
X'D': Configured to respond to a 64K address size, and enables internal windowing of
memory.
X'E': Configured to respond to a 32K address size, and enables internal windowing of
memory.
X'F': Configured to respond to a 16K address size, and enables internal window
Description
pnr25.chapt04.01
August 14, 2000
Preliminary