ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 241

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
8.2: BCACH Status Register
The bits in this register reflect the current status of the cache. See Note on Set/Clear Type Registers on page
93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt04.01
August 14, 2000
7
Bit(s)
7
6
5
4
3
2
1
0
6
5
POOLS invalidation of dirty lines
Write Hit on Multiple Lines
Read Hit on Multiple Lines
Negative Ack from VIMEM
Collision on Cache Line 3
Collision on Cache Line 2
Collision on Cache Line 1
Collision on Cache Line 0
4
3
2
Function
1
0
8 bits
Clear/Set
XXXX 1008 and 00C
X’00’
None
When this bit is set, it indicates that POOLS requested that the cache logic invalidate a
line that was dirty. This is usually an indication that a buffer was freed by the software
before data written out to the buffer had been flushed to memory. This may or may not
be an error condition.
When this bit is set, the cache logic has detected a write hit to multiple lines. This indi-
cates an internal logic error in the cache.
When this bit is set, the cache logic has detected a read hit to multiple lines. This indi-
cates an internal logic error in the cache.
When set, the cache logic has detected a negative acknowledgment from the Virtual
Memory Logic entity. This indicates that a virtual buffer boundary was crossed and a new
real buffer was needed to map the requested address space into, but no real buffer was
available. In addition to setting this status bit, the cache logic writes the pattern
X’zzzzzBAD’ into the header of the packet at offset X’C’ where zzzzz is the offset of the
failing write into the packet.
When this bit is set, the cache logic has detected a collision in cache line 3. This is a sit-
uation where another entity in IBM3206K0424 was accessing an area of memory that
was contained in one of the cache lines that was dirty. Further information for problem
diagnosis is latched in the memory controller logic when this condition is detected.
When this bit is set, the cache logic has detected a collision in cache line 2.
When this bit is set, the cache logic has detected a collision in cache line 1.
When this bit is set, the cache logic has detected a collision in cache line 0.
Description
IBM Processor for Network Resources
The Bus DRAM Cache Controller (BCACH)
Page 241 of 676
IBM3206K0424