ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 257

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
9.7: POOLS Pointer Queues DRAM Tail Pointer Offset Address Register
The POOLS Pointer Queues DRAM Tail Pointer Offset Address Register indicates the offset address in
DRAM where the tail of the queue starts. This address, however, is only relative to the DRAM portion of the
queue. Unless a ‘no cache frames to be written through’ state is in effect, the actual tail of the queue is in the
cache.
These 19 bits on write represent the offset to the address in DRAM of the tail of the queue relative to the
DRAM base address. On a read, the address in DRAM of the pointer is returned. This pointer is adjusted
every time a cache frame boundary is crossed and a cache update cycle is completed to write through the
additional queue elements. Since each memory reference contains four indices this allows for 128K index
locations possible in the queue.
Length
Type
Address
Power on Value
Restrictions
pnr25.chapt04.01
August 14, 2000
16 bits
Read/Write
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
During normal operations this register is to be used as a read only register. This regis-
ter defaults to zero at initialization. It is assumed that the queues start on the maximum
size queue boundary. These registers should be setup at initialization time. This regis-
ter is cleared when the POOLS Pointer Queues DRAM Lower Bound Address Register
is written to.
XXXX 3028
XXXX 302C
XXXX 3030
XXXX 3034
XXXX 3038
X’00 01 C0 00’
X’00 02 00 00’
X’00 02 40 00’
X’00 02 60 00’
X’00 02 70 00’
IBM Processor for Network Resources
Buffer Pool Management (POOLS)
Page 257 of 676
IBM3206K0424