ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 137

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
2.3: INTST Control Register
This register is used to control various IBM3206K0424 functions. See Note on Set/Clear Type Registers on
page 93 for more details on addressing.
Length
Type
Address
Restrictions
Power on Reset value
pnr25.chapt04.01
August 14, 2000
18 17 16 15 14 13 12 11 10
Bit(s)
18
17
16
15
14
13
12
11
Delayed Interrupts - Assume a
64bit PCI target
Delayed Interrupts - Assume a
32bit PCI target
Delayed Interrupts - Swap words
control
Delayed Interrupts - Enable inter-
rupt 1
Delayed Interrupts - Enable inter-
rupt 2
Delayed Interrupts - Endian Bit
Delayed Interrupts - Route inter-
rupt 2 to interrupt 1
Delayed Interrupts - returned sta-
tus word type
Name
18 bits
Clear/Set
XXXX 0408 and 0C
None
X’0010200’
9
8
7
This bit set will help the mastering logic determine how to best move data to a 64-bit
PCI target. This bit is set when software has system knowledge of its targets.
This bit set will help the mastering logic determine how to best move data to a 32-bit
PCI target. This bit is set when software has system knowledge of its targets.
This bit determines the word order of the status word dma transfer for delayed ints.
The default value of ’1’ is to swap the words. A value of ’0’ will not swap them.
When set, the delayed int mechanism for int 1 is enabled.
When set, the delayed int mechanism for int 2 is enabled.
This bit determines the endian of the status word DMA transfer for delayed ints. When
this bit is set, the endian is little. The default of ‘0’ is big endian.
When set, the int 2 signal is routed and raised as int 1. This bit allows both sets of int
masks in intst to be used, while still using only a single hardware int. When set, both
delayed int's should be enabled if they are being used.
When this bit is set, the INTST Interrupt Source word will be anded with the corre-
sponding enable register. Otherwise, the INTST Interrupt Source register alone will be
returned.
6
5
4
3
2
1
0
Description
IBM Processor for Network Resources
Interrupt and Status/Control (INTST)
Page 137 of 676
IBM3206K0424