ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 29

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
Preliminary
IBM Processor for Network Resources
Subsystem Blocks
The IBM Processor for Network Resources provides the host bus interfacing, memory management for
buffers and control, cell segmentation and reassembly, and PHY hardware control for an ATM adapter.
External Memory consists of a number of SRAM modules, or two SDRAM arrays used for the storage of
packet data and the control structures used by the IBM3206K0424. Both the Packet and Control Memory
arrays consist of two 32-bit wide banks.
When running at 102Mb/s or slower (full duplex aggregate throughput), a single array of memory can be
used. Both control and data store are contained in this single array of memory. For a detailed description of
the external memory organization refer to The DRAM Controllers (COMET/PAKIT) on page 184.
The PHY (Physical) Layer interface connects to several available hardware support devices. This layer of
hardware converts a parallel data stream into a serial data stream to be shipped to and from the PMD layer.
The PHY and PMD end of a card design can be implemented as one of several encoding schemes and
speeds, supporting both copper and fibre optic serial links. The interface will support the ATM Forum “Utopia
spec,” the PMC chip, and a 25Mb/s serial interface to the IBM UTP solution. (See Standards Compliance on
page 23 for documents which describe these interfaces.)
The PMD (Physical Media Dependent) Layer interface connects to the line drivers and receivers. This could
be either a copper or a fibre optic transceiver.
pnr25.chapt01.01
Subsystem Blocks
August 14, 2000
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