ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 42

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
PCI Bus Interface Pin Descriptions
DRAM Memory Bus Interface
Page 42 of 676
Quantity
1. S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low
32
32
1
4
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
must drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one
clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be
provided by the central resource.
PAD64(63-32)
PCBE64(7-4)
PCBE(3-0)
PAD(31-0)
MDEVSEL
Pin Name
MFRAME
MREQ64
MACK64
PPAR64
MSERR
MPERR
PIDSEL
MTRDY
MSTOP
MIRDY
MINTA
MINT2
MREQ
MGNT
PPAR
O/D or S/T/S
Input/Output
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
S/T/S
O/D
O/D
T/S
T/S
T/S
IN
IN
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycle Frame is driven by the current master to indicate the beginning and duration of an
access.
Bus Command and Byte Enables are multiplexed on the same PCI pins. During address
phase they define the bus command; during data phase they define the byte enables.
System Error reports address parity errors, data parity errors on the Special Cycle com-
mand, or any other system error where the result will be catastrophic.
Address and Data are multiplexed on the same pins. A bus transaction consists of one
address phase and one or more data phases.
Parity is even parity across ad(31-0) and C/BE(3-0). Parity generation is required by all
PCI agents.
Parity Error is for reporting data parity errors during all PCI bus transactions except Spe-
cial Cycle.
Interrupt A is used to request an interrupt.
This is an interrupt line that will go active low when sources within the IBM3206K0424 go
active. It can be optionally connected to PCI interrupt B. See Entity 2: on page 135 for
more details.
Initialization Device Select is a chip select during configuration transactions.
Device Select indicates the driving device has decoded its address as the target of the
current transaction.
Target Ready signals the target agent’s ability to complete the current data phase of the
transaction.
Initiator Ready indicates the bus master’s ability to complete the current data phase.
Stop indicates the current target is requesting the master to stop the current transaction.
Receives the Bus Grant line after a request has been made.
Requests the bus for an initiator transfer.
Address and Data are multiplexed on the same pins and provide 32 additional bits. Also,
these pins are multiplexed with the ENSTATE outputs, which allow debug of various inter-
nal state machines and signals.
Bus Command and Byte Enables are multiplexed on the same PCI pins for 64-bit transfer
support.
Request 64-bit transfer. Has the same timing as MFRAME.
Acknowledge 64-bit transfer. Has the same timing as MDEVSEL.
Parity Upper DWORD is the even parity bit that protects MAD64(63-32) and PCBE(7-4).
When not on a PCI bus supporting 64 bits, this will drive ENSTATE outputs.
Pin Description
pnr25.chapt02.01
August 14, 2000
Preliminary