ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 22

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
IBM3206K0424
IBM Processor for Network Resources
Ordering Information
Conventions
The bit notation is non-IBM, meaning that bit zero is the least significant bit and bit 31 is the most significant
bit for a four-byte word.
The internal addressing view of the IBM3206K0424 registers and memory is big endian. In most cases, a sys-
tem will wire its PCI bus interface to make the register view transparent, that is, the most significant bit in this
specification will be the most significant bit in the register. If registers are read and written 32 bits at a time
(which is the only way to access many of the registers), the endian-ness should not be a programming issue
with respect to the registers.
The IBM3206K0424 DMA controller can transfer data in either big endian or little endian mode. See General
Purpose DMA (GPDMA) on page 175 for details.
Numeric notation is as follows:
Conventions
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• Hexadecimal values are usually preceeded by x or X. For example: X’0B00’. For individual registers,
• Binary values in text are either spelled out (zero and one) or appear in quotation marks.
• Binary values in the Default and Description columns of the register sections are often isolated from text
Address values are hexadecimal without any special markings. For example, XXXX 1C3C.
For example: ‘10101’.
as in this example:
0: No action on read access
1: Auto-reset interrupt request register upon read access
IBM3206K0424
Part Number
Network Resource Manager
Description
pnr25.chapt01.01
August 14, 2000
Preliminary

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