ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 440

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
16.8: CHKSM Control Register
The various bits in this register control the mode in which the checksum entity operates. See Note on
Set/Clear Type Registers on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
On-chip Checksum and DRAM Test Support (CHKSM)
Page 440 of 676
12 11 10 9
bit(s)
12
11
10
9
8
CL-FF -- Clear to All Ones
EX-AL -- Expose Alignment
HI-LO -- Hi Lo Word
SW-SUM -- Swap Checksum
IN-SUM -- Invert Checksum
8
7
6
Name
5
13 bits
Clear/Set
XXXX 0A28 and 2c
X’00’
None
4
3
2
1
When this bit is set, the CHKSM TCP/IP Checksum Data Register is set to 0xffff when
it is cleared. When this bit is cleared, the CHKSM TCP/IP Checksum Data Register is
set to ’0’. This option should be used if the TCP/IP checksum should never be set to ’0’
(0xffff is ‘0’ also).
When this bit is set, the internal checksum alignment is exposed for reading/writing.
For writes, bit 16 of the write data is used to set the internal alignment. For reads, the
alignment is exposed in bit 16 or bit 0 depending on the value of the HI-LO bit in this
register. This can be useful if doing non-consecutive multiple part check sums (need to
preserve alignment between chunks). When this bit is cleared, the internal checksum
aliment is not exposed. It is always cleared when the CL-IP bit in this register is set.
Normally, the internal alignment is calculated and maintained across consecutive
check sums.
When this bit is set, the checksum data register data is placed in the most significant
16 bits of the 32-bit value read. When this bit is cleared, the checksum data register
data is placed in the least significant 16 bits of the 32-bit value read. This bit does not
affect how writes to the checksum data register occur; the data from the least signifi-
cant 16 bits is always used.
When this bit is set, the checksum data register data is byte-swapped when read.
When this bit is cleared, the checksum data register data is read normally.
There are also new checksum data register addresses that can be read that do the
same thing as this control bit. This bit is depreciated.
When this bit is set, the checksum data register data is inverted when read. When this
bit is cleared, the checksum data register data is read normally.
There are also new checksum data register addresses that can be read that do the
same thing as this control bit. This bit is depreciated.
0
Description
pnr25.chapt05.01
August 14, 2000
Preliminary