ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 110

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
1.13: PCINT Endian Control Register
This register allows control and status to the big/little endian address selection. It controls the byte order
across the PCI bus. See bit definitions.
Length
Type
Address
Restrictions
Power on Reset value
The IOP Bus Specific Interface Controller (PCINT)
Page 110 of 676
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
31-29
28-24
Bit(s)
23-5
4
3
2
1
0
Reserved
Same as the definitions for bits 4-0
Reserved
Byte Swap For Expansion ROM
(on-card flash)
Reverse the byte order for the
VPD Data Register
Byte Swap for Configuration
Registers
Byte Swap for Register Access
(Memory or I/O space)
Byte Sway for Memory
See bits 4 - 0
Name
32 bits
Read/Write
XXXX 0058
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle.
X’00000000’
Reserved.
Reserved.
When this bit is set to ’1’, the bytes of an internal Expansion ROM access (big
endian view) will be swapped to and from the PCI interface.
When this bit is set to ’1’, the bytes of the Vital Product Data Interface - Word 2 reg-
ister access will be swapped in reverse order to which bits 2 or 1 are set.
When this bit is set to ’1’, the bytes of an internal Configuration register access (big
endian view) will be swapped to and from the PCI interface.
When this bit is set to ’1’, the bytes of an internal register access (big endian view)
will be swapped to and from the PCI interface.
When this bit is set to ’1’, the bytes of an internal Packet Memory access (big endian
view) will be swapped to which bits 2 or 1 are set.
Reserved
Description
9
8
7
6
5
4
pnr25.chapt04.01
August 14, 2000
3
Preliminary
2
1
0