ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 395

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
Preliminary
13.15: RXQUE Event Latency Timer Register
Used to specify the event latency time interval. This register is specified in 15 ns intervals. When a new event
is placed on an rxq, the event latency timer is started (if not already started). When this timer expires, the
event latency timer expired status bit is set, and the timer is stopped. The status bit must be reset before the
timer is started again. Every time the status register (or prioritized status) is accessed, the timer is stopped. If
this register is written while the timer is running, the new value takes effect immediately. If this register is set
to ’0’, the latency timer does not run.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt05.01
August 14, 2000
32 bits
Read/Write
XXXX 1C20
X’00000000’
None
IBM Processor for Network Resources
Receive Queues (RXQUE)
Page 395 of 676
IBM3206K0424

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