ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 464

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Processor Core (PCORE)
Page 464 of 676
16-15
Bit(s)
26
25
24
23
22
21
20
19
18
17
15
14
13
12
11
10
9
8
7
6
Control Memory Access Priority
High on Latency Timer Max
Crossing
Control Memory Access Priority
High on Write FIFO Full
Control Memory Access Priority
High
Packet Memory Access Priority
High on Latency Timer Max
Crossing
Packet Memory Access Priority
High on Write FIFO Full
Packet Memory Access Priority
High
Lock Arbit on Error
PCI Master Write Around FIFO
Disable
Packet Memory Write Around
FIFO Disable
Control Memory Write Around
FIFO Disable
Reserved
Disable Xfer Abort on Pseudo
Core Reset
JTAG Hold Most Recent Error Sta-
tus
Cobra Hold Most Recent Event
Status
Auto Ack on Hang or Error
Detected
FDMA Virtual Memory Error Nor-
mal/Critical Interrupt
DCache Virtual Memory Error Nor-
mal/Critical Interrupt
Memory Lock Normal/Critical
Interrupt
64 Bit DCR Primitives
Target Access Dead Man Timer
Master Disable
Serial Port Receive Interrupt Prior-
ity
Name
When set, Control Memory accesses will switch to high priority when the Control Mem-
ory latency counter crosses the high priority crossover register value.
When set, Control Memory accesses will switch to high priority when the Control Mem-
ory write around FIFO is full.
When set, Control Memory accesses will be at high priority always.
When set, Packet Memory memory accesses will switch to high priority when the
Packet Memory latency counter crosses the high priority crossover register value.
When set, Packet Memory accesses will switch to high priority when the Packet Mem-
ory write around FIFO is full.
When set, Packet Memory accesses will be at high priority always.
When set to ’1’, will cause a lock command to be issued to arbit to halt the memory
subsystem.
Disables the write around buffer for PCI Master. When enabled, write data from either
the ICACH or DCACH is buffer through this FIFO on writes.
Disables the write around buffer for Packet Memory. When enabled, write data from
either the ICACH or DCACH is buffer through this FIFO on writes.
Enables the write around buffer for Control Memory. When enabled write data from
either the ICACH or DCACH is buffer through this FIFO on writes.
Reserved
When this bit is written to ’1’, transfer aborts on Pseudo resets are disabled; when ’0’,
the core master state machines will be put into idle.
When this bit is written to ’0’, the JTAG error status register will free run. When set to
’1’ it will hold the most recent error status.
When this bit is written to ’1’, Cobra Core hold it most recent internal event status.
When set to ’0’ it will free run.
When this bit is written to ’0’, PCORE will not auto ack on hang or error. This may
leave the processor in a totally stuck state. However corrupted information may be
stopped from entering the processor. When set to ’1’ and hang or error conditions
manifest reads may return garbage and write data may be lost BUT the processor
should not be stopped cold.
When this bit is written to ’0’, PCORE will treat an IBM3206K0424 virtual memory write
error as a critical interrupt. When it is ’1’, this condition will be treated as a normal inter-
rupt.
When this bit is written to ’0’, PCORE will treat an IBM3206K0424 virtual memory write
error as a critical interrupt. When it is ’1’, this condition will be treated as a normal inter-
rupt.
When this bit is written to ’0’, PCORE will treat memory locked as a critical interrupt.
When it is ’1’, this condition will be treated as a normal interrupt.
When set, the three DCR primitives work in 64-bit mode. In this mode, the first access
to the primitive register is to the upper 32 bits. The second reference is to the lower 32
bits. The second access triggers the completion of the operation at the destination.
When set, this will disable all of the Target Access Dead Man Timers: PCI Master,
Control Memory, Packet Memory, IBM3206K0424 Registers and DCR.
When set, this will cause a the receive interrupt to be a Critical Interrupt. When not set,
it is a regular interrupt.
Description
pnr25.chapt05.01
August 14, 2000
Preliminary