ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 205

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
6.7: VIMEM Packet Memory Offset
This register contains the number that will be added by the VIMEM access logic to all accesses of real Packet
Memory that occur. In a high performance configuration (separate control and packet store), this register
should be written to all zeros to indicate that all accesses of real Packet Memory do not require any additional
offset to be added. In a medium performance configuration (combined control and packet store), this register
should be loaded with a value that indicates the logical partitioning between control and packet storage. If for
instance, a single bank of 2 meg was configured and this register was loaded with X’00100000’ (1 meg), then
all accesses to real Packet Memory would be forced into the 1-meg to 2-meg range.
Length
Type
Address
Power On Value:
Restrictions
6.8: VIMEM Maximum Buffer Size
This register is used by the Virtual Memory logic to determine if an access to a virtual buffer falls into the
region of the buffer that can be accessed. If a virtual buffer read or write accesses an offset in a virtual buffer
that is greater than the contents of this register, the Virtual Memory logic can be configured to halt and gener-
ate an interrupt. The power up value of all ones causes this check to be disabled. This register is intended to
provide the user with a means of providing additional protection to accesses of the virtual buffers. For exam-
ple, if this register is loaded with X’FF8’, all memory access up to and including the byte at address X’FFF’ are
allowed. Any access of offset X’1000’ or above will cause an exception.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt04.01
August 14, 2000
32 bits
Read/Write
XXXX 0D3C
X’0000 0000’
This register should only be loaded with a non-zero value if a medium performance
configuration (combined control and packet store) exists. The value loaded must be
between zero and the maximum of the total amount of memory in the single bank,
and it must be on a 128KB boundary. Any time the value in this register is changed,
the related base registers must be reloaded because the value loaded into them is
affected by the contents of this register during the load operation. The related regis-
ters are the Virtual Buffer Map Base Address Register and all five real buffer base
registers.
17 bits
Read/Write
XXXX 0D34
X’1 FFF8’
All address logic based on this register only recognizes eight-byte words in mem-
ory. For this reason, the low three bits of this register are not implemented and are
always forced to ‘0’.
IBM Processor for Network Resources
ATM Virtual Memory Logic (VIMEM)
Page 205 of 676
IBM3206K0424