ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 258

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
9.8: POOLS Pointer Queues DRAM Lower Bound Address Register
The POOLS Pointer Queues DRAM Lower Bound Address Register indicates the address in DRAM where
the queue data structure is initially started. When the queue reaches the maximum address allowed for in the
upper bound register, it wraps back around to the address specified in this register. This implements the
queue in a circular buffer.
These 32 bits represent the address in DRAM where the queue begins and eventually wraps to. At initializa-
tion, this register and the POOLS Pointer Queues DRAM Tail Pointer Offset Address Register and the
POOLS Pointer Queues DRAM Head Pointer Offset Address Register must be equal.
Length
Type
Address
Power on Value
Restrictions
Buffer Pool Management (POOLS)
Page 258 of 676
32 bits
Read/Write
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
Buffer Size 0
Buffer Size 1
Buffer Size 2
Buffer Size 3
Virtual Packets/
Buffer Size 4
During normal operations, this register is to be used as a read only register. This regis-
ter should be setup at initialization time. The size of the DRAM queue storage which is
formed with the lower and upper bounds is constrained in its size. It can be written
when the diagnostic mode bit is set, otherwise the write is ignored. Note that if the max-
imum queue length exceeds the space available in the circular buffer, data corruption
will occur when the actual queue length exceeds the maximum queue space available.
XXXX 303C
XXXX 3040
XXXX 3044
XXXX 3048
XXXX 304C
X’00 01 C0 00’
X’00 02 00 00’
X’00 02 40 00’
X’00 02 60 00’
X’00 02 70 00’
pnr25.chapt04.01
August 14, 2000
Preliminary