ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 96

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
The IOP Bus Specific Interface Controller (PCINT)
Page 96 of 676
19-16
15-10
Bit(s)
23
22
21
20
9
8
6
5
4
3
2
1
0
7
PCI Spec
15-10
3-0
7
6
5
4
9
8
7
6
5
4
3
2
1
0
Fast Back-to-Back Capable
Reserved
66MHz Capable
Capabilities List
Reserved
Reserved
Fast Back-to-Back Enable
SERR Enable
Wait Cycle Control
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate
Enable
Special Cycles
Bus Master Enable
Memory Space Enable
I/O Space Enable
Name
Defaults to ’1’ unless by Crisco code. See Entity 15: on page 428 for
details.
Defaults to ’0’ unless set by Crisco. See Entity 15: on page 428 for details.
Defaults to ’1’ unless set by Crisco. See Entity 15: on page 428 for details.
This bit on indicates that this device implements the pointer for a New
Capabilities linked list at the offset 34th. See the PCI spec revision 2.2 for
more details on New Capabilities. Defaults to ’1’ unless set by Crisco
code. See Entity 15: on page 428 for details for more on Crisco.
Reserved
Reserved
This bit can be set to a value, but is ignored by this DMA master since it
never drives these types of cycles. This slave, as indicated by bit 23, how-
ever, can handle fast back-to- back addresses to it. Initialization software
will set this bit if all targets are fast back-to-back capable.
If this bit is ’1’, the SERR driver is enabled.
This bit is hard-wired to ’0’ because stepping is not supported by this mas-
ter.
When this bit is ’1’, normal action is taken when a parity error is detected.
When it is ’0’, any parity errors detected are ignored and normal operation
is continued.
This bit is not implemented.
This bit is not implemented.
This bit is set to ’0’, and will not monitor Special Cycle operations.
If this bit is ’1’, this device will be allowed to act as a bus master.
If this bit is ’1’, this device will respond to memory space accesses.
If this bit is ’1’, this device will respond to I/O space accesses.
Description
pnr25.chapt04.01
August 14, 2000
Preliminary