ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 200

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Entity 6: ATM Virtual Memory Logic (VIMEM)
This entity is responsible for adjustment of all addresses provided to the memory control entities. All
addresses can be categorized into three distinct types, based entirely upon the location of the requested
address with respect to the three base registers defined in this entity. The three types of addresses are
referred to as control, real packet, and virtual packet addresses.
All memory requests arriving on the Control Memory bus are handled as Control Memory accesses, and sim-
ply have the contents of the Control Memory Base Register subtracted from them before being passed on to
the Control Memory Entity. When the processor accesses memory, the cache controller compares the
requested address to the Real Packet Memory Base Register and if the address is less than the base regis-
ter, the request is routed to the Control Memory bus; otherwise it is routed to the Packet Memory bus. All
requests arriving on the Packet Memory bus are compared to the Virtual Memory Base Address Register. If
the address of the request is less than the base register, the contents of the Real Packet Memory Base Reg-
ister are subtracted from the address and this address is passed on to the Packet Memory Control Entity. If
the requested address is greater than or equal to the base register, a more complex, but flexible scheme is
used to determine the real address to provide to the Packet Memory Control Entity. For a detailed explanation
of the virtual address generation scheme refer to Virtual Memory Overview on page 248 and the accompany-
ing figures.
6.1: VIMEM Virtual Memory Base Address
This register defines the starting address of the virtual address space used to manage incoming and outgoing
frames. Any time an access is made to Virtual Memory that falls within the defined bounds of Virtual Memory,
the contents of this register are subtracted from the virtual address to derive the true offset into Virtual Mem-
ory. This true offset, along with the known length of all virtual buffers, allows the index of the specific virtual
buffer to be derived by the Virtual Memory access hardware. This index can then be used to access the real
buffer map associated with this virtual buffer.
Length
Type
Address
Power On Value
Restrictions
ATM Virtual Memory Logic (VIMEM)
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31-17
Bit(s)
16-0
These bits contain the upper 15 bits of the base address of Virtual Memory.
These bits are forced to ’0’ because the Virtual Memory base address must start on a 128K byte boundary.
Base Address of Virtual Memory
32 bits
Read/Write
XXXX 0D10
X’0040 0000’
The start of virtual address space must begin on a 128KB boundary. For this rea-
son, the lowest 17 bits of this register are forced to ’0’ and are not implemented.
Writes of any value to the low 17 bits of this register are ignored, and a read always
returns ’0’ for the low 17 bits.
Description
128KB Boundary Restriction
9
8
7
6
5
4
pnr25.chapt04.01
August 14, 2000
3
Preliminary
2
1
0