ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 490

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
17.43: PCORE Address Translation Offset Address Facilities
The PCORE Address Translation Offset Address Facilities provides the offset that is added to the Cobra Real
Address to create the target subsystem address.
When an address is issued from the Cobra Core core it is accompanied by four target translation bits. The
translation bits indicate which translation facility is to be used to translate the processor "real" physical
address into a target system actual address. This grouping provides for the offset addresses for each target
memory system. The offset is added to the Cobra Real Address to create the target system address. The
following is a list of targets, each with their own translation facilities.
’0000’
’0001’
’0010’
’0011’
’0100’
’0101’
’0110’
’0111’
’1000’
’1001’
’1010’
’1011’
’1100’
’1101’
’1110’
’1111’
PCORE Address Translation Offset Address Facilities:
Length
Type
Address
Processor Core (PCORE)
Page 490 of 676
OCM (Translation provided for in the MMUs)
Packet Memory View 0
Packet Memory View 1
Packet Memory View 2
IBM3206K0424 Registers
Control Memory View 0
Control Memory View 1
Control Memory View 2
PCI Master Access (Non IBM3206K0424) View 0
PCI Master Access (Non IBM3206K0424) View 1
PCI Master Access (Non IBM3206K0424) View 2
PCI Master Access (Non IBM3206K0424) View 3
Control/Packet View 0
Control/Packet View 1
Control/Packet View 2
Control/Packet View 3
32 bits
Read/Write
Packet Memory Offset View 0
Packet Memory Offset View 1
Packet Memory Offset View 2
IBM3206K0424 Registers Offset View 0
Control Memory Offset View 0
Control Memory Offset View 1
Control Memory Offset View 2
PCI Master Offset View 0
PCI Master Offset View 1
XXXX 4048
XXXX 404C
XXXX 4050
XXXX 4054
XXXX 4058
XXXX 405C
XXXX 4060
XXXX 4064
XXXX 4068
pnr25.chapt05.01
August 14, 2000
Preliminary