ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 400

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
13.19: RXQUE Control Register
Used to set RXQUE modes. See Note on Set/Clear Type Registers on page 93 for more details on address-
ing. This register contains the mode bits that specify how RXQUE is to operate.
Length
Type
Address
Power On Value
Restrictions
Receive Queues (RXQUE)
Page 400 of 676
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
30-12
Bit(s)
31
11
10
9
8
7
6
5
4
3
Reset FIFO
Reserved
Assume 64-bit PCI
Assume 32-bit PCI
Enable swap words on PCI
Enable swap bytes on PCI
Always route error events
Enable chip overflow events
Memory select
Inhibit enqueues
Timestamp mode
Name
32 bits
Clear/Set
XXXX 1C00 and C04
X’00000300’
None
Reserved
When this bit is set, the internal FIFO is flushed, and this bit is reset. The result is this
bit will always be read as a ’0’. This bit can only be set in diagnostic mode.
Reserved.
This bit is automatically set at power-on.
This bit is automatically set at power-on.
When this bit is set, all error events are routed to the error queue even if rx bad frames
(bit2) is turned on. When cleared, error events are only routed to the error queue if rx
bad frames is turned off. This bit allows the user to keep bad frames in time sequence
with good frames or to route them to the error queue. The clear state of this bit is code
compatible with previous versions of the processor.
When set, the chip level counter overflow events are surfaced.
When this bit is set, RXQUE will use Packet Memory instead of Control Memory to
store the event queues.
When this bit is set, the enq state machine will not accept any new enq requests. This
should be used in extreme cases as it holds off all enqueues indefinitely.
When this bit is set, timestamp events are inserted before each real event. The times-
tamps correspond to when the event happened on chip. When this bit is off, times-
tamps can still be read from the timestamp register. The timestamps would correspond
to when the event was dequeued in this scenario.
Description
9
8
7
6
5
4
pnr25.chapt05.01
August 14, 2000
3
Preliminary
2
1
0