ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 382

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
13.1: RXQUE Lower Bound Registers
These registers specify the lower bound of the corresponding receive queue data structure. The head and tail
of the receive queue are initialized when this register is written. When the receive queue wraps past the upper
bound, it wraps back to the value in the lower bound register, thus implementing the receive queue as a circu-
lar buffer.
When this register is written, the corresponding receive queue is essentially reset. This is because the head,
tail, and length of the queue are all reset.
The length of the RXQUE Lower Bound Register is 64 bits if all three conditions, below, are met; otherwise,
the length is 32 bits.
Length
Type
Address
Power on Value
Restrictions
Receive Queues (RXQUE)
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• System Receive-Queue in the RXQUE Properties Register is set.
• System-Memory Select in the RXQUE Properties Register indicates "PCI Memory."
• Enable Master 64-bit Addressing in the PCINT 64bit Control Register is set.
32 or 64 bits
Read/Write
Queue 0
Queue 1
Queue 2
Queue 3
Queue 4
Queue 5
Queue 6
Queue 7
Queue 8
Queue 9
Queue 10
Queue 11
Queue 12
Queue 13
Queue 14
Queue 15
X'0000000000000000'
During normal operations, these registers are read only. These registers can only
be written when the diagnostic bit has been set in the control register.
The lower bound registers must be at least 1K aligned (low order 10 bits not
writable). The alignment should also correspond to the size specified in the upper
bound register. For example, it should be 4K aligned if the upper bound specifies
4K size.
XXXX 1800
XXXX 1840
XXXX 1880
XXXX 18C0
XXXX 1900
XXXX 1940
XXXX 1980
XXXX 19C0
XXXX 1A00
XXXX 1A40
XXXX 1A80
XXXX 1AC0
XXXX 1B00
XXXX 1B40
XXXX 1B80
XXXX 1BC0
pnr25.chapt05.01
August 14, 2000
Preliminary