ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 125

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.23: Power Management Program Control
This register contains the control register for power management signalling.
Length
Type
Address
Restrictions
Power on Reset Value
(Big Endian)
Power on Reset Value
(Little Endian)
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31-16
15-14
13-12
11-10
Bit(s)
7-3
9
8
2
Reserved
Reserved
Asserted Ext_PME# Power-
States
Deasserted Ext_PME# Power-
States
Reserved
Set External PME# Input
Receiver Polarity
Enable External PME# Input
Enable PowerState Change
Interrupt
Name
Reserved
32 bits
Read/Write
XXXX 0090
Can be written or read during configuration cycle
Address Control Register on page 111), or as an I/O cycle. This register is documented as big endian,
but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian
Control Register.
X’00000000’
X’00000000’
Reserved
These bits reflect what power state the Ext_PME# pin will indicate that it is in when the
Ext_PME# is asserted.
These bits reflect what power state the Ext_PME# pin will indicate that it is in when the
Ext_PME# is de-asserted. Also, these are the default bits read back for the pmi2 power-
states bits 1-0 when Ext_PME# is not enabled.
Reserved
Setting this bit to ’1’ will make the chip input called Ext_PME# to be used as a positive
active signal. Otherwise it is negative active.
Setting this bit to ’1’ will enable the chip input called Ext_PME# to be used as a source to
driver the PM# state.
Reserved
Setting this bit to ’1’ will enable a change of power states to cause an interrupt bit to turn on
in INTST.
or
memory cycle when enabled (see PCINT Base
Description
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
9
8
7
Reserved
6
5
4
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IBM3206K0424
3
2
1
0