ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 95

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.2: PCINT Config Word 1
The Status register is used to record status information for the PCI bus related events. Writing ’1’ to a bit in
this register will reset that bit. The Command register provides coarse control over a device’s ability to gener-
ate and respond to PCI cycles. Access type of the Command register is read/write. See bit definitions.
Length
Type
Address
Restrictions
Power on Reset value
(Big Endian)
Power on Reset value
(Little Endian)
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
26-25
Bit(s)
31
30
29
28
27
24
PCI Spec
10-9
15
14
13
12
11
8
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
DEVSEL Timing
Data Parity Detected
32 bits
Read/Write and Read/Reset
XXXX 0004
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
X’02B00000’
X’0000B002’
Name
Reserved
This bit is set by the device whenever it detects a parity error, even if par-
ity error handling is disabled (as controlled by bit 6 of PCINT Configuration
Word 1).
This bit is set whenever the device asserts SERR.
This bit is set by a master device whenever its transaction is terminated
with master-abort, except for Special Cycle.
This bit is set by a master device whenever its transaction is terminated
with target-abort.
This bit is set by a target device whenever its transaction is terminated
with target-abort.
These bits are hard-wired to ’01’, assuming medium address decode.
This bit is implemented by this bus master. It is set when this agent
asserts PERR or observeS PERR asserted, AND this agent setting the bit
acted as the bus master for the operation in which the error occurred,
AND bit 6 of PCINT Configuration Word 1 is set.
Reserved
The IOP Bus Specific Interface Controller (PCINT)
IBM Processor for Network Resources
Description
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IBM3206K0424
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