R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 138

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
12.5
Table 12.6
NOTES:
Table 12.7
• Instruction with 2-byte operation code
• Instruction with 1-byte operation code
ADD.B:S
OR.B:S
STNZ
CMP.B:S
JMPS
MOV.B:S
Instructions other than the above
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
An address match interrupt request is generated immediately before executing the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used for a break function of the debugger. When
using the on-chip debugger, do not set an address match interrupt (the AIER, RMAD0 to RMAD1 registers, and
relocatable vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. The AIER0 and AIER1 bits in the AIER0
register can select to enable or disable the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register (the appropriate return address is not pushed on the stack). When returning from the address
match interrupt, return by one of the following:
Table 12.6 lists the Value of PC Saved to Stack when Address Match Interrupt is Acknowledged. Figure 12.19
shows the Registers AIER and RMAD0 to RMAD1.
1. Refer to the 12.1.6.7 Saving a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Address Match Interrupt 0
Address Match Interrupt 1
•
•
Change the content of the stack and use the REIT instruction.
Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowledged.
And then use a jump instruction.
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code
below each syntax. Operation code is shown in the bold frame in the diagrams.
Address Match Interrupt
#IMM8,dest SUB.B:S
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest STZX
#IMM8,dest PUSHM
#IMM8
#IMM,dest (However, dest = A0 or A1)
Value of PC Saved to Stack when Address Match Interrupt is Acknowledged
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Indicated by RMADi Register (i = 0 or 1)
Page 116 of 501
JSRS
#IMM8,dest AND.B:S
#IMM81,#IMM82,dest
src
#IMM8
(2)
(2)
AIER0
AIER1
POPM
#IMM8,dest
#IMM8,dest
dest
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
PC Value Saved
RMAD0
RMAD1
12. Interrupts
(1)