R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 326

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.11
16.2.2
• When SSUMS bit = 0
• When SSUMS bit = 1 (4-wire bus communication
16.2.2.1
(clock synchronous communication mode)
mode), BIDE bit = 0 (standard mode) and MSS bit = 0
(operates as slave device)
The SSTRSR register is the shift register to transmit and receive the serial data.
When the transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), the bit 7 in the SSTDR register is transferred to the bit 0 in the
SSTRSR register.
Connecting association between the data I/O pin and SSTRSR register (SS shift register) changes according to
a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. Also,
connecting association changes according to the BIDE bit in the SSMR2 register.
Figure 16.11 shows an Association between Data I/O Pins and SSTRSR Register.
SSTRSR Register
SSTRSR Register
SS Shift Register (SSTRSR)
Association between Data I/O Pins and SS Shift Register
Association between Data I/O Pins and SSTRSR Register
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SSO
SSI
SSO
SSI
• When SSUMS bit = 1 (4-wire bus communication mode),
• When SSUMS bit = 1 (4-wire bus communication mode),
BIDE bit = 0 (standard mode) and MSS bit = 1 (operates
as master device)
BIDE bit = 1 (bidirectional mode)
SSTRSR Register
SSTRSR Register
16. Clock Synchronous Serial Interface
SSO
SSI
SSO
SSI