R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 306

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 15.8
Figure 15.9
15.1.1
15.1.2
Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer
clock polarity.
Figure 15.9 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format.
Polarity Select Function
LSB First/MSB First Select Function
• When UFORM Bit in U0C0 Register = 0 (LSB first)
• When UFORM Bit in U0C0 Register = 1 (MSB first)
NOTE:
RXD0
RXD0
CLK0
TXD0
CLK0
TXD0
Transfer Clock Polarity
Transfer Format
CLK0
CLK0
• When the CKPOL Bit in the U0C0 Register = 0 (output transmit data at the falling
• When the CKPOL Bit in the U0C0 Register = 1 (output transmit data at the rising
1. The above applies when the CKPOL bit in the U0C0 register is set to 0
RXD0
RXD0
TXD0
TXD0
edge and input the receive data at the rising edge of the transfer clock)
edge and input the receive data at the falling edge of the transfer clock)
NOTES:
1. When not transferring, the CLK0 pin level is “H”.
2. When not transferring, the CLK0 pin level is “L”.
(output transmit data at the falling edge and input receive data at the
rising edge of the transfer clock).
(1)
(2)
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D0
D0
D7
D7
D0
D0
D0
D0
D1
D1
D6
D6
D1
D1
D1
D1
D2
D2
D5
D5
D2
D2
D2
D2
D3
D3
D4
D4
D3
D3
D3
D3
D4
D4
D3
D3
(1)
(1)
D4
D4
D4
D4
D5
D5
D2
D2
D5
D5
D5
D5
D6
D6
D1
D1
D6
D6
D6
D6
D7
D7
D0
D0
D7
D7
D7
D7
15. Serial Interface