R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 141

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Controlling an interrupt with the I flag, IR bit, ILVL0 to ILVL2 bits and IPL by Timer RD (channel 0), Timer RD
(channel 1), clock synchronous serial I/O with chip select and I
maskable interrupts. However, since an interrupt source is generated based on multiple interrupt request sources,
there are the following differences from other maskable interrupts:
Refer to chapters of each peripheral function (14.3 Timer RD, 16.2 Clock Synchronous Serial I/O with Chip
Select (SSU) and 16.3 I
Refer to 12.1.6 Interrupt Control for the interrupt control register.
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When bits in the enable register corresponding to set bits in the status register to 1 are set to 1 (enable
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
When either bits in the status register or bits in the enable register corresponding to bits in the status register, or
both of them are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is
not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not
set to 0 although 0 is written to the IR bit.
Since each bit in the status register is not automatically set to 0 even if the interrupt is acknowledged.
Therefore, the IR bit is not also automatically set to 0 when the interrupt is acknowledged. Set each bit in the
status register to 0 in the interrupt routine. Refer to the status register figure how to set each bit in the status
register to 0.
When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is
set to 1, the IR bit remains 1.
When multiple bits in the enable register are set to 1, determine by the status register which request source
causes an interrupt.
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2
C Bus Interface) for the status register and enable register.
2
C bus interface is the same as that by other
12. Interrupts