R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 332

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.15
16.2.5.3
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode).
During the data receive, the clock synchronous serial I/O with chip select operates as described below. When
the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and
inputs data.
When the clock synchronous serial I/O with chip select is set as a salve device, it outputs data synchronized
with the input clock. When the clock synchronous serial I/O with chip select is set as a master device, it outputs
a receive clock and starts receiving by performing dummy read on the SSRDR register.
After the 8-bit data is received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (enables RXI and
OEI interrupt request), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). The clock synchronous serial I/O with chip select outputs a clock for receiving
8-bit data and stops. After that, set the RE bit in the SSER register to 0 (disables receive) and the RSSTP bit to
0 (receive operation is continued after receiving the 1-byte data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (enables receive), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error occurs: OEI) and the operation is stopped. When the ORER bit is set to 1, receive can not be performed.
Confirm that the ORER bit is set to 0 before restarting receive.
Figure 16.16 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
• When SSUMS bit = 0 (clock synchronous communication mode), CPHS bit = 0 (data download at
Process by
program
even edges) and CPOS bit = 0 (“H” when clock stops)
SSCK
Data Reception
Reception (Clock Synchronous Communication Mode)
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
SSI
1
0
1
0
Dummy read in
SSRDR register
Page 310 of 501
b0
RXI interrupt request
generation
1 frame
Read data in SSRDR
register
b7
b0
RXI interrupt request
generation
1 frame
Set RSSTP bit to 1
b7
16. Clock Synchronous Serial Interface
b0
Read data in
SSRDR register
RXI interrupt request
generation
b7