R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 386

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 17.9
Hardware LIN Clear the status flags
Timer RA Set to start a pulse width measurement
Timer RA Read the count status flag
Hardware LIN Set to start Synch Break detection
Hardware LIN Read the RXD0 input status flag
Hardware LIN Read the Synch Break detection flag
TSTART bit in the TRACR register ← 1
TCSTF flag in the TRACR register
Example of Header Field Reception Flowchart (2)
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
LSTART bit in the LINCR register ← 1
RXDSF flag in the LINCR register
SBDCT flag in the LINST register
Page 364 of 501
RXDSF = 1?
SBDCT = 1?
TCSTF = 1?
YES
YES
YES
A
B
NO
NO
NO
Timer RA waits until the timer
starts counting.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
Hard ware LIN wait until the RXD0
input for UART0 is masked.
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during
this time is input directly to UART0.
One to two cycles of the CPU clock
and zero to one cycle of the timer
RA count source are required after
the LSTART bit is set to 1 before the
RXDSF flag is set to 1.
After this, input to timer RA and
UART0 is enabled.
Hard ware LIN detect a Synch
Break.
The interrupt of timer RA may be
used.
When Synch Break is detected,
timer RA is reloaded with the
initially set count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the
initially set count value and waits
until the next “L” level is input.
One to two cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (Unmasked after
Synch Break is detected), timer RA
may be used in timer mode after
the SBDCT flag in the LINST
register is set to 1 and the RXDSF
flag in the LINCR register is set to
0.
17. Hardware LIN