R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 369

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.43
16.3.4.3
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when the MST bit
in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are shown below.
ICDRR register
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the CKS0 to CKS3 bits in the
(2) The output of the receive clock stars by setting the MST bit to 1 when the transfer clock is output.
(3) Data is transferred from the ICDRS to ICDRR registers and the RDRF bit in the ICSR register is set to
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the following
ICDRS register
ICSR register
by program
RDRF bit in
MST bit in
TRS bit in
Process
ICCR1 register and set the MST bit (initial setting).
1, when the receive is completed. Since the following-byte data is enabled to receive when the MST bit
is set to 1, the continuous clock is output. The continuous receive is enabled by reading the ICDRR
register every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock while the
RDRF bit is set to 1, the AL bit in the ICSR register is set to 1. At this time, the former receive data is
retained in the ICDRR register.
receive operation) and read the ICDRR register. The SCL signal is fixed “H” after the receive of the
following-byte data is completed.
(input)
ICCR1
ICCR1
SDA
SCL
Receive Operation
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
1
0
1
0
1
0
(2) Set MST bit to 1
(when transfer clock is output)
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b0
1
b1
Data 1
2
(3) Read ICDRR register
b6
7
b7
8
b0
Data 1
1
16. Clock Synchronous Serial Interface
Data 2
b6
7
(3) Read ICDRR register
b7
8
Data 2
1
b0
Data 3
2