R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 223

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.53
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2
NOTES:
1.
2.
3.
This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR
register is set to 1 (external clock input enabled).
This bit is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate synchronously).
Registers TRDCR0 to TRDCR1 in Output Compare Function
b1 b0
Bit Symbol
TRDCR0
TRDCR1
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
Page 201 of 501
TCK0
TCK1
TCK2
Count source selection bit
External clock edge
selection bit
TRDi counter clear selection
bit
Address
Bit Name
0140h
0150h
(2)
b2 b1 b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input
1 1 0 : fOCO40M
1 1 1 : Do not set
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set
b7 b6 b5
0 0 0 : Disable clear (free-running operation)
0 0 1 : Clear by the compare match in the
0 1 0 : Clear by the compare match in the
0 1 1 : Synchronous clear (clear
1 0 0 : Do not set
1 0 1 : Clear by the compare match in the
1 1 0 : Clear by the compare match in the
1 1 1 : Do not set
TRDGRAi register
TRDGRBi register
simultaneously w ith other channel
counter)
TRDGRCi register
TRDGRDi register
(3)
After Reset
Function
(1)
00h
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW