R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 415

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 18.25
18.12.2 Transmission
CANbus
TrmReq bit
TrmActive bit
SentData bit
CAN0 successful
transmission
interrupt
TrmState bit
TrmSucc bit
MBOX bit
Figure 18.25 shows the Timing of Transmit Sequence.
(1) If the TrmReq bit in the C0MCTLi register (i = 0 to 15) is set to 1 (Transmission slot) in bus idle state,
(2) If the arbitration is lost after starting transmitting, the TrmActive and TrmState bits are set to 0.
(3) If the transmission is successful without lost arbitration, the SentData bit in the C0MCTLi register is set
(4) When next transmission is performed, set the SentData and TrmReq bits to 0 and check that they are set
the TrmActive bit in the C0MCTLi register and the TrmState bit in the C0STR register are set to 1
(During transmission), and the CAN module starts transmitting a message.
to 1 (Transmission is successfully completed) and TrmActive bit in the C0MCTLi register is set to 0
(Waiting for bus idle or completion of arbitration). When the interrupt enable bits in the C0ICR register
are set to 1 (Interrupt enabled), CAN0 successful transmission interrupt request is generated and the
MBOX and TrmSucc bits in the C0STR register change.
to 0. Then, set the TrmReq bit to 1 by a program.
Timing of Transmit Sequence
i = 0 to 15
(1)
Page 393 of 501
(1)
(1)
SOF
(2)
(2)
ACK
EOF
(3)
(3)
(3)
IFS
Transmission slot
SOF
No.
(4)
18. CAN Module