R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 336

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.2.6
16.2.6.1
4-wire bus communication mode is a mode which communicates with the 4-wire bus; a clock line, data input
line, data output line and chip select line. This mode includes bidirectional mode in which the data input line
and data output line function as a single pin.
The data input line and output line are changed according to the setting of the MSS bit in the SSCRH register
and the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and
SS Shift Register. In this mode, association between the clock polarity, phase and data can be set by the CPOS
and CPHS bits in the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock
Polarity, Phase, and Data.
When the clock synchronous serial I/O with chip select is set as a master device, the chip select line controls
output. When the clock synchronous serial I/O with chip select is set as a slave device, the chip select line
controls input. When the clock synchronous serial I/O with chip select is set as master device, the chip select
line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in the SSMR2
register. When the clock synchronous serial I/O with chip select is set as a slave device, the chip select line set
the SCS pin as an input pin by setting the CSS1 and CSS0 bits in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is
performed using the MSB-first.
Figure 16.18 shows an Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive, set
the TE bit in the SSER register to 0 (disables transmit) and the RE bit in the SSER register to 0 (disables
receive) and initialize the clock synchronous serial I/O with chip select.
When communication mode and format are changed, set the TE bit to 0 and the RE bit to 0 before changing.
Setting the RE bit to 0 does not change the contents of the RDRF and ORER flags, and the contents of the
SSRDR register.
Operation in 4-Wire Bus Communication Mode
Initialization in 4-Wire Bus Communication Mode
Page 314 of 501
16. Clock Synchronous Serial Interface