R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 321

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.6
SS Status Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
7.
When reading 1 and w riting 0, the CE, ORER, RDRF, TEND and TDRE bits are set to 0.
When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is
set to 1 if “L” is applied to the SCS
When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operates as slave device) is set to 0 (operates as slave device) and the SCS
changes the level from “L” to “H” during transfer, the CE bit is set to 1.
Indicates overrun error occurs and receive completes by error w hen receive. When the next serial data receive is
completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the ORER bit is
set to 1 (overrun error occurs), do not transmit or receive w hile the ORER bit is set to 1.
The RDRF bit is set to 0 w hen reading out the data from the SSRDR register.
The TEND and TDRE bits are set to “0” w hen w riting the data to the SSTDR register.
The TDRE bit is set to 1 w hen setting the TE bit in the SSER register to 0 (disables transmit).
When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
b3 b2 b1
SSSR Register
b0
(7)
Bit Symbol
(b4-b3)
Symbol
SSSR
ORER
RDRF
TEND
TDRE
Page 299 of 501
(b1)
CE
—
—
Conflict error flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Overrun error flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Receive data register full
(1,4)
Transmit end
Transmit data empty
_____
pin input. Refer to 16.2.7 SCS
Address
Bit Name
00BCh
(1,5)
(1)
(1)
(1,5,6)
0 : No conflict error occurs
1 : Conflict error occurs
0 : No overrun error occurs
1 : Overrun error occurs
0 : No data in SSRDR register
1 : Data in SSRDR register
0 : The TDRE bit is set to 0 w hen transmitting
1 : The TDRE bit is set to 1 w hen transmitting
0 : Data is not transferred from the SSTDR to
1 : Data is transferred from the SSTDR to SSTRSR
_____
the end of the bit in transmit data
the end of the bit in transmit data
SSTRSR registers
registers
Pin Control and Arbitration for more information.
16. Clock Synchronous Serial Interface
After Reset
Function
00h
(2)
(3)
_____
pin input
RW
RW
RW
RW
RW
RW
—
—