R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 52

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 5.3
Figure 5.4
Option Function Select Register
Internal reset
signal
CPU clock
Address
(internal address
signal)
RESET pin
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
3.
fOCO-S
NOTES:
1 1
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
To use the pow er-on reset, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset).
If the block including the OFS register is erased, FFh is set to the OFS register.
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Reset Sequence
OFS Register
1
10 cycles or more are needed
Bit Symbol
fOCO-S clock × 32 cycles
CSPROINI
ROMCP1
LVD1ON
WDTON
ROMCR
(b5-b4)
Symbol
OFS
(b1)
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—
—
Start time of flash memory
(CPU clock × 14 cycles)
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bits
Voltage detection circuit
start bit
Count source protect
mode after reset select
bit
(1)
(1)
(2)
Address
Bit Name
(2)
0FFFFh
CPU clock × 28 cycles
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to 1
0 : ROM code protect disabled
1 : ROMCP1 enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to 1
0 : Voltage monitor 1 reset enabled after reset
1 : Voltage monitor 1 reset disabled after reset
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
0FFFCh
Before Shipment
0FFFDh
Function
FFh
(3)
0FFFEh
Content of reset vector
RW
RW
RW
RW
RW
RW
RW
RW
5. Resets