R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 256

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Table 14.31
i = 0 or 1, j = either A, B, C or D
NOTE:
Count Sources
Count Operations
PWM Operations
Count Start Condition
Count Stop Conditions
Interrupt Request Generation
Timing
TRDIOA0 Pin Function
TRDIOB0 Pin Function
TRDIOD0 Pin Function
TRDIOA1 PIn Function
TRDIOC1 Pin Function
TRDIOB1 Pin Function
TRDIOD1 Pin Function
TRDIOC0 Pin Function
INT0 Pin Function
Read from Timer
Write to Timer
Selection Functions
1. After a count starts, the PWM period is stable.
Item
Complementary PWM Mode Specifications
Page 234 of 501
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Set the TCK2 to TCK0 bits in the TRDCR1 register to the same value (same count
source) as the TCK2 to TCK0 bits in the TRDCR0 register.
Increment or decrement
The TRD0 and TRD1 registers are decremented with the compare match in the
TRD0 and TRDGRA0 registers during increment. The TRD1 register is set from
0000h to FFFFh during decrement, the TRD0 and TRD1 registers are incremented.
PWM period: 1/fk × (m + 2 - p) × 2
Dead time: p
Active level width of normal-phase: 1/fk × (m - n - p + 1) × 2
Active level width of counter-phase: 1/fk × (n + 1 - p) × 2
Write 1 (count starts) to the TSTART0 and TSTART1 bits in the TRDSTR register.
Write 0 (count stops) to the TSTART0 and TSTART1 bits in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
(The PWM output pin holds output level before the count stops.)
• Compare match (the content in the TRDi register matches with the content in the
• The TRD1 register undeflows
Programmable I/O port or TRDCLK (external clock) input
PWM output 1 normal-phase output
PWM output 1 counter-phase output
PWM output 2 normal-phase output
PWM output 2 counter-phase output
PWM output 3 normal-phase output
PWM output 3 counter-phase output
Output inversed every 1/2 period of PWM
Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output Forced
• The active level of normal-phase and counter-phase and initial output level
• Transfer timing from the buffer register selected
• A/D trigger generated
fk: Frequency of count source
m: Setting value in the TRDGRA0 register
n: Setting value in the TRDGRB0 register (PWM output 1)
p: Setting value in the TRD0 register
TRDGRji register.)
Cutoff )
selected individually.
Counter-phase
Setting value in the TRDGRA1 register (PWM output 2)
Setting value in the TRDGRB1 register (PWM output 3)
Normal-phase
n + 1 - p
n + 1
m + 2 - p
p
m - p - n + 1
(1)
Specification
(When “L” is selected for the active level)
14. Timers