R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 148

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
13.1
Table 13.2
NOTES:
Count Source
Count Operation
Period
Count Start Condition
Reset Condition of Watchdog
Timer
Count Stop Condition
Operation at the Time of
Underflow
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
1. The watchdog timer is reset when writing 00h to the WDTR register before writing FFh. The
2. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write 0 to the bit 0
prescaler is reset after the MCU is reset. Some errors occur by the prescaler for the period of the
watchdog timer.
of the address 0FFFFh using a flash programmer.
Count Source Protection Mode Disabled
Item
Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Page 126 of 501
CPU clock
Decrement
Division ratio of prescaler(n) x count value of watchdog timer(32768)
n: 16 or 128 (selected by WDC7 bit in WDC register)
e.g.When the CPU clock is 16 MHz and prescaler is divided by 16, the
The WDTON bit
of watchdog timer after reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
• When the WDTON bit is set to 0 (watchdog timer starts automatically
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to 0
• When the PM12 bit in the PM1 register is set to 1
The watchdog timer and prescaler stop after reset and the count
starts by writing to the WDTS register
after exiting)
The watchdog timer and prescaler start counting automatically after
reset
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
reset)
Watchdog timer interrupt
period is approximately 32.8 ms
(2)
in the OFS register (0FFFFh) selects the operation
Specification
CPU clock
13. Watchdog Timer
(1)