R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 351

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.28
IIC Bus Status Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
7.
Each bit is set to 0 when reading 1 bef ore writing 0.
This f lag is enabled in slav e receiv e mode of the I
When two or more master dev ices attempt to occupy the bus at nearly the same time, if the I
and the data which the IIC transmits is dif f erent, the AL f lag is set to 1 and the bus is occupied by the other masters.
The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receiv e acknowledge bit is set to 1, transf er is
halted)
The RDRF bit is set to 0 when reading data f rom the ICDRR register.
The TEND and TDRE bits are set to 0 when writing data to the ICDRT register.
When accessing the ICSR register continuously , insert one or more NOP instructions between the instructions to access it.
b3 b2 b1
ICSR Register
b0
Bit Symbol
Symbol
NACKF
Page 329 of 501
STOP
RDRF
TEND
TDRE
ICSR
ADZ
AAS
(7)
AL
General call address
recognition flag
Slave address recognition
flag
Arbitration lost flag /
overrun error flag
Stop condition detection
flag
No acknow ledge detection
flag
Receive data register full
Transmit end
Transmit data empty
(1)
(1)
(1,4)
Address
Bit Name
00BCh
(1,6)
2
(1,2)
C bus f ormat.
(1)
(1,6)
(1,5)
When detecting the general call address, this flag
is set to 1.
This flag is set to 1 w hen the first frame follow ing
start condition matches the SVA0 to SVA6 bits in
the SAR register in slave receive mode. (Detect the
slave address and generate call address)
When the I
that arbitration is lost in master mode. In the
follow ing case, this flag is set to 1.
• When the internal SDA signal and SDA pin
• When the start condition is detected and the
This flag indicates that an overrun error occurs
w hen the clock synchronous format is used
In the follow ing case, this flag is set to 1.
• When the last bit of the follow ing data is
When the stop condition is detected after the frame
is transferred, this flag is set to 1
When no acknow ledge is detected from receive
device w hen transmit, this flag is set to 1
When receive data is transferred from ICDRS to
ICDRR registers, this flag is set to 1
When the 9th clock of the SCL signal w ith the I
bus format w hile the TDRE bit is set to 1, this flag is
set to 1
This flag is set to 1 w hen the final bit of the
transmit frame is transmitted w ith the clock
synchronous format
In the follow ing cases, this flag is set to 1
• Data is transferred from ICDRT to ICDRS
• When setting the TRS bit in the ICCR1
• When generating the start condition
• When changing from slave receive mode to
level do not match at the rise of the SCL signal
in master transmit mode
SDA pin is held “H” in master transmit /
receive mode
received w hile the RDRF bit is set to 1
registers and ICDRT register is empty
register to 1 (transmit mode)
(including retransmit)
slave transmit mode
2
C bus format is used, this flag indicates
16. Clock Synchronous Serial Interface
After Reset
0000X000b
Function
2
C bus Interf ace monitors the SDA pin
(3)
2
C
RW
RW
RW
RW
RW
RW
RW
RW
RW