R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 493

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
22.3
22.3.1
Notes on Timers
•
•
•
•
•
•
•
•
•
Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count
starts.
Even if the prescaler and timer RA is read out in 16-bit units, these registers are read by 1 byte in the MCU.
Consequently, the timer value may be updated during the period these two registers are being read.
In pulse width measurement mode and pulse period measurement mode, the TEDGF and TUNDF bits in
the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain
unchanged when 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR
register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is
executed. At the time, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the
MOV instruction.
When changing to pulse width measurement mode and pulse period measurement mode from other mode,
the contents of the TEDGF and TUNDF bits are indeterminate. Write 0 to the TEDGF and TUNDF bits
before the count starts.
The TEDGF bit may be set to 1 by timer RA prescaler underflow which is generated for the first time since
the count starts.
When using the pulse period measurement mode, leave two periods or more of timer RA prescaler
immediately after count starts, and set the TEDGF bit to 0.
The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count stops.
During this time, do not access registers associated with timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit retains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops)
while the count is performing. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA
NOTE:
When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
Notes on Timer RA
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, TRA
Page 471 of 501
(1)
(1)
other than the TCSTF bit.
other than the TCSTF bit. Timer RA
22. Usage Notes