R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 342

IC R8C/23 MCU FLASH 48LQFP

R5F21236KFP#U0

Manufacturer Part Number
R5F21236KFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/23r
Datasheet

Specifications of R5F21236KFP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
16MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21236KFP#U0R5F21236KFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21236KFP#U0R5F21236KFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21236KFP#U0R5F21236KFP#W4
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.21
16.2.7
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode), and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), Set the MSS bit in the SSCRH register to 1 (operates as
a master device) and check the arbitration of the SCS pin before starting serial transfer. If the clock synchronous
serial I/O with chip select detects that the synchronized internal SCS signal is held “L” in this period, the CE bit
in the SSSR register to 1 (a conflict error occurs) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 16.21 shows an Arbitration Check Timing.
A future transmit operation is not performed while the CE bit is set to 1. Set the CE bit to 0 (a conflict error does
not occur) before a transmit is started.
(synchronization)
SSCRH register
Transfer start
Internal SCS
SCS Pin Control and Arbitration
SCS output
MSS bit in
SCS input
Arbitration Check Timing
CE
Page 320 of 501
1
0
High-impedance
During arbitration detection
Data write to
SSTDR register
Maximum time of SCS internal
synchronization
16. Clock Synchronous Serial Interface

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