R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 259

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.89
Timer RD Function Control Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of
the TRDPMR register.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).
Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).
enabled.
b3 b2
b1 b0
TRDFCR Register in Complementary PWM Mode
Bit Symbol
TRDFCR
ADTRG
Symbol
STCLK
ADEG
PWM3
CMD0
CMD1
OLS0
OLS1
Page 237 of 501
Combination mode selection bit
Normal-phase output level selection
bit (in reset synchronous PWM mode
or complementary PWM mode)
Counter-phase output level selection
bit (in reset synchronous PWM mode
or complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge selection bit
(in complementary PWM mode)
External clock input selection bit
PWM3 mode selection bit
Address
Bit Name
013Ah
(4)
(1,2)
b1 b0
1 0 : Complementary PWM mode
1 1 : Complementary PWM mode
Other than above : Do not set
0 : Initial output “H”
1 : Initial output “L”
0 : Initial output “H”
1 : Initial output “L”
0 : Disable A/D trigger
1 : Enable A/D trigger
0 : A/D trigger is generated at the
1 : A/D trigger is generated at the
0 : External clock input disabled
1 : External clock input enabled
This bit is disabled in complementary PWM
mode.
Active level “L”
Active level “H”
Active level “L”
Active level “H”
compare match in the TRD0 and
TRDGRA0 register
underflow in the TRD1
register
(transfer from the
buffer register to the general
register at the underflow in
the TRD1 register.)
(transfer from the
buffer register to the general
register at the compare match w ith
the TRD0 and TRDGRA0 registers.)
After Reset
10000000b
Function
(3)
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW