R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 349

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.26
IIC Bus Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
3.
4.
5.
6.
0
Rew rite betw een transfer frames. When w rite values other than 000b, w rite w hen the SCL signal is “L”.
When w rite to the BC0 to BC2 bits, w rite 0 to the BCWP bit using the MOV instruction.
After data including the acknow ledge bit is transferred, bits b2 to b0 are automatically set to 000b. When the start
condition is detected, these bits are automatically set to 000b.
Do not rew rite w hen the clock synchronous serial format is used.
The setting value is enabled in master mode of the I
w hen the clock synchronous serial format is used.
Set to 0 w hen the I
ICMR Register
Bit Symbol
Symbol
BCWP
WAIT
2
ICMR
Page 327 of 501
BC0
BC1
BC2
(b4)
(b5)
MLS
C bus format is used.
—
—
Bit counter 2 to 0
BC w rite protect bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Reserved bit
Wait insertion bit
MSB-first / LSB-first select
Address
Bit Name
00BAh
(5)
2
C bus format. It is disabled in slave mode of the I
I
w hen read out and data bit numbers of transfer to
the next w hen w rite)
b2 b1 b0
0 0 0 : 9 bits
0 0 1 : 2 bits
0 1 0 : 3 bits
0 1 1 : 4 bits
1 0 0 : 5 bits
1 0 1 : 6 bits
1 1 0 : 7 bits
1 1 1 : 8 bits
Clock synchronous serial format (w hen read, read
the remaining transfer bit numbers and w hen w rite,
w rite 000b.)
b2 b1 b0
0 0 0 : 8 bits
0 0 1 : 1 bit
0 1 0 : 2 bits
0 1 1 : 3 bits
1 0 0 : 4 bits
1 0 1 : 5 bits
1 1 0 : 6 bits
1 1 1 : 7 bits
When rew rite to the BC0 to BC2 bits, w rite 0
simultaneously.
When read, its content is 1.
Set to 0
0 : No w ait
1 : Wait
0 : Data transfer by MSB-first
1 : Data transfer by LSB-first
2
C bus format (remaining transfer bit numbers
(Transfer data and acknow ledge bit
(After the falling of the clock for the final
consecutively)
data bit, “L” period is extended for tw o
transfer clocks)
(3)
(2,4)
16. Clock Synchronous Serial Interface
After Reset
00011000b
(1,2)
Function
(6)
2
C bus format or
RW
RW
RW
RW
RW
RW
RW
RW
—