R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 323

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.8
Figure 16.9
SS Transmit Data Register
SS Receive Data Register
Port Mode Register
b7
NOTE:
b7
b7 b6 b5 b4
1. The SSRDR register maintains the receive data before the overrun error occurs w hen the ORER bit in the SSSR
0 0
register is set to 1 (overrun error occurs). When an overrun error occurs, the receive data may contain errors and
therefore, should be discarded.
b3 b2
0
0
b1
PMR Register
Registers SSTDR and SSRDR
0
b0
b0
b0
0
Store the receive data.
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen receiving 1-byte data to the SSTRSR register. At this time, the follow ing receive is
possible. The continuous receive is possible by the SSTRSR and SSRDR registers.
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and the transmit is started
w hen detecting the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmit from the
SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed can be read, after w riting to the SSTDR register.
Bit Symbol
U1PINSEL
Symbol
SSRDR
(b3-b0)
(b6-b5)
Symbol
SSTDR
Symbol
IICSEL
Page 301 of 501
PMR
—
—
Reserved bits
Port TXD1/RXD1 sw itch bit
Reserved bits
SSU/I
2
C bus sw itch bit
(1)
Address
Address
Address
Bit Name
00BFh
00BEh
00F8h
Function
Function
Set to 0
0 : I/O port P6_6, P6_7
1 : TXD1, RXD1
Set to 0
0 : SSU function selects
1 : I
2
C bus function selects
16. Clock Synchronous Serial Interface
After Reset
After Reset
After Reset
Function
FFh
FFh
00h
RW
RW
RW
RW
RW
RW
RO
—
—