R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 308

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
15.2
Table 15.4
i = 0 or 1
NOTE:
Transfer Data Formats
Transfer Clocks
Transmit Start Conditions
Receive Start Conditions
Interrupt Request
Generation Timing
Error Detection
The UART mode allows transmit and receive data after setting the desired bit rate and transfer data format.
Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode.
1. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR
bit in the S0RIC register remains unchanged.
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
Page 286 of 501
• Character bit (transfer data): selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: selectable from odd, even, or none
• Stop bit: selectable from 1 or 2 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n + 1))
• CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
• Before receive starts, the following are required
• When transmitting, one of the following conditions can be selected
• When receiving
• Overrun error
• Framing error
• Parity error
• Error sum flag
• Before transmit starts, the following are required
fj = f1, f8, f32 n = setting value in U0BRG register: 00h to FFh
fEXT: Input from CLK0 pin n = setting value in UiBRG register: 00h to FFh
- TE bit in UiC1 register is set to 1 (transmit enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
- RE bit in UiC1 register is set to 1 (receive enabled)
- Detects start bit
- UiIRS bit is set to 0 (transmit buffer empty):
- UiIRS bit is set to 1 (transfer ends):
When transferring data from the UARTi receive register to UiRB register
(when receive ends)
This error occurs if serial interface starts receiving the following data
before reading the UiRB register and receiving the bit one before the last
stop bit of the following data
This error occurs when the number of stop bits set are not detected
This error occurs when parity is enabled, the number of 1’s in parity and
character bits do not match the number of 1’s set
This flag is set is set to 1 when any of the overrun, framing, and parity
errors is generated
when transferring data from the UiTB register to UARTi transmit register
(when transmit starts)
when serial interface completes transmitting data from the UARTi
transmit register
(1)
Specification
15. Serial Interface